ROOT / COMPUTE // DECODED
// NODE 01 · COMPUTE · 18 accelerators indexed

The silicon
behind it all.

AI isn't a software story — it's power, cooling and silicon. This is the compute index: the accelerators training and serving frontier models, who makes them, and the physical infrastructure they run on. Real specs, primary sources, zero hype.

$0B
2025 AI capex
0%
Accelerator share · NVIDIA
3–5NM
Leading process node
1.2GW
Largest campuses
// Spec comparison

Who's ahead,
by the numbers.

The frontier accelerators, compared on the spec that actually bottlenecks frontier models. The leader is lit in green. Pick a metric.

// higher is better · HBM capacity per accelerator · sources: NVIDIA GTC, AMD, vendor datasheets
// Generational climb

A chip a year,
memory doubling.

HBM per GPU across NVIDIA's data-center line. The near-annual cadence — Hopper → Blackwell → Rubin — is why frontier labs buy whole racks.

// HBM capacity per flagship GPU (GB) · Rubin marks the HBM3e → HBM4 transition
// The silicon

AI accelerator index

The chips training and serving the frontier. Search, filter by maker, or sort any column. This table is the database on display.

Accelerator Maker Process Memory (GB) BW (TB/s) Year What it's for
// — shown · full sourced index with FP4 throughput + $/GPU is free & open
// NVIDIA roadmap

Blackwell → Vera Rubin

A new AI platform roughly every year, each about doubling low-precision throughput and memory.

2022 · shipped
Hopper
H100 / H200 — the GPU that trained the first frontier LLMs.
80–141 GB HBM3/3e
2024 · shipping
Blackwell
B200 / GB200 — two dies fused, 208B transistors, native FP4. NVL72 = one rack, 1.4 EF FP4.
192 GB HBM3e
2025 · shipping
Blackwell Ultra
GB300 — memory to 288 GB, 1.5× FP4 inference. The test-time-compute chip.
288 GB HBM3e
● 2026 · now
Vera Rubin
Vera Arm CPU (88 cores) + Rubin GPU, first HBM4. NVL144 ≈ 3.6 EF FP4, 3.3× a GB300 rack.
288 GB HBM4 · 22 TB/s
2027 · roadmap
Rubin Ultra
NVL576 — more dies per package on TSMC 2 nm, aimed at gigawatt "AI factories."
2 nm-class
// The physical layer

What compute
actually needs

Chips are only the visible tip — the real constraints are wafers, watts and heat.

// Newsroom · newest in compute

Rubin arrives

What's shipping at the leading edge of AI silicon right now. all stories →